parallel to serial converter using mux and flip flops

A counter as defined in claim 3 including an additional multiplexed flip/flop for receiving the signal from the toggle and for providing a parallel data clock signal at a parallel data clock rate.ĥ. A counter as defined in claim 2 in which the counter is comprised of a two-bit gray code counter having its output connected to a multiplexed flip/flop forming an AND gate for providing a predetermined logic output signal when a count signal output from the gray code counter is 11 2, and a multiplexed flip/flop forming a toggle for receiving an output signal from the AND gate, toggling to divide the output signal from the AND gate by two, and providing a resulting signal to a further multiplexed flip/flop for generating the enable signal therefrom.Ĥ. A counter as defined in claim 1 in which the counter includes a circuit for providing the enable signal upon counting at least four input clock pulses.ģ.

(d) a controller for generating the enable signal and for applying the enable signal to the shift register and parallel word latch, said controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.Ģ. (c) a circuit for receiving a serial clock signal and for providing the serial clock signal to the shift register to enable shifting of the stored bits to an output as the serial stream of bits, and (b) a shift register for receiving the parallel data words and for storing bits of a parallel data word in a series of shift register stages upon receipt of a first enable signal, and for providing a serial stream of bits at a serial clock rate,

(a) a parallel word latch for receiving a series of words comprised of parallel data words, A parallel to serial converter comprising:

Parallel to serial converter using mux and flip flops